CVE-2023-46835

/// Technical description

The current setup of the quarantine page tables assumes that the

quarantine domain (dom_io) has been initialized with an address width

of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels.

However dom_io being a PV domain gets the AMD-Vi IOMMU page tables

levels based on the maximum (hot pluggable) RAM address, and hence on

systems with no RAM above the 512GB mark only 3 page-table levels are

configured in the IOMMU.

On systems without RAM above the 512GB boundary

amd_iommu_quarantine_init() will setup page tables for the scratch

page with 4 levels, while the IOMMU will be configured to use 3 levels

only, resulting in the last page table directory (PDE) effectively

becoming a page table entry (PTE), and hence a device in quarantine

mode gaining write access to the page destined to be a PDE.

Due to this page table level mismatch, the sink page the device gets

read/write access to is no longer cleared between device assignment,

possibly leading to data leaks.

/// Remediation

Check the references section for vendor advisories, patches, and mitigation guidance. If immediate patching is not possible, review the CVSS vector to understand the attack surface and apply compensating controls such as network segmentation or access restrictions.

/// References