CVE-2024-26670

/// Technical description

In the Linux kernel, the following vulnerability has been resolved:

arm64: entry: fix ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD

Currently the ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround isn't

quite right, as it is supposed to be applied after the last explicit

memory access, but is immediately followed by an LDR.

The ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD workaround is used to

handle Cortex-A520 erratum 2966298 and Cortex-A510 erratum 3117295,

which are described in:

* https://developer.arm.com/documentation/SDEN2444153/0600/?lang=en

* https://developer.arm.com/documentation/SDEN1873361/1600/?lang=en

In both cases the workaround is described as:

| If pagetable isolation is disabled, the context switch logic in the

| kernel can be updated to execute the following sequence on affected

| cores before exiting to EL0, and after all explicit memory accesses:

|

| 1. A non-shareable TLBI to any context and/or address, including

| unused contexts or addresses, such as a `TLBI

/// Remediation

Check the references section for vendor advisories, patches, and mitigation guidance. If immediate patching is not possible, review the CVSS vector to understand the attack surface and apply compensating controls such as network segmentation or access restrictions.

/// References