CVE-2026-74276

Technical Description

In the Linux kernel, the following vulnerability has been resolved:

spi: xilinx: use FIFO occupancy register to determine buffer size

The method the driver uses to determine the size of the FIFO has a

problem. What it currently does is this:

It stops the SPI hardware and writes to the TX FIFO register until TX

FIFO FULL asserts in the status register. But the hardware does not only

have the FIFO, it also has a shift register which can hold a byte. This

can be seen, when writing a byte to the FIFO (while the SPI hardware is

stopped,) the TX FIFO EMPTY is still empty. So, if we have a FIFO size

of 16 for example, the current method returns a 17.

This is a problem, at least when using the driver in irq mode. The same

size determined for the TX FIFO is also assumed for the RX FIFO. When a

SPI transaction wants to write the amount of the FIFO size or more

bytes, the following happens, for example with 16 bytes FIFO size:

The driver stops the SPI hardware and writes 17 bytes to the TX FIFO

Remediation

Check the references section for vendor advisories, patches, and mitigation guidance. If immediate patching is not possible, review the CVSS vector to understand the attack surface and apply compensating controls such as network segmentation or access restrictions.

References